1. Field of the Invention
The present invention relates to semiconductor devices and a manufacturing method thereof-, and more particularly to semiconductor devices each having a stacked structure formed by selectively removing a polycrystalline silicon film and a silicon oxide film, employing the same mask, and to a manufacturing method thereof. The present invention is particularly applicable to a dynamic type random access memory having memory cells of stacked capacitor structures.
2. Description of the Background Art
Since the present invention can attain the most desirable effect when applied to a dynamic type random access memory (hereinafter referred to as a DRAM) having memory cells of stacked capacitor structures, a DRAM having memory cells of the stacked capacitor structures will be described. The DRAM has been already well known. FIG. 3 is a block diagram illustrating one example of the entire configuration of the conventional DRAM.
Referring to FIG. 3, the DRAM comprises a memory cell array 100 including a plurality of memory cells, which are of a storage portion, a row decoder 200 and a column decoder 300 connected to their respective address buffers selecting addresses of the memory cells, and an input/output interface portion including a sense amplifier connected to an input/output circuit. The plurality of memory cells being the storage portion are provided in a matrix of a plurality of rows and columns. Each of the memory cells is connected to a corresponding word line connected to the row decoder 200 and to a corresponding bit line connected to the column decoder 300, thereby constituting the memory cell array 100. A memory cell is selected by the respective one of the word lines and bit lines selected by the row decoder 200 and the column decoder 300 in response to a row address signal and a column address signal externally supplied. Data is written in the memory cell selected, and the data stored in the memory cell is read. Instructions of the data reading/writing are carried out by read/write control signals applied to a control circuit.
The data is stored in the memory cell array 100 of N (=n.times.m) bits. Address information of the memory cell in which read/write are carried out is stored in the row and column address buffers, and by selection of a particular word line by the row decoder 200 (selection of one from n word lines), m-bit memory cells are coupled to the sense amplifiers via the bit lines. Next, by selection of a particular bit line by the column decoder 300 (selection of one from m-bit lines), one of the sense amplifiers is coupled to the input/output circuit to carry out read or write according to the instructions of the control circuit.
FIG. 4 is an equivalent circuit diagram of one memory cell 10 of the DRAM illustrated for the description of write/read operations of the memory cells. According to this figure, the memory cell 10 comprises a field effect transistor Q and a capacitor Cs. The field effect transistor Q has a gate electrode connected to the word line 20, one source/drain electrode connected to one electrode of the capacitor Cs, and the other source/drain electrode connected to the bit line 30. In data writing, since the field effect transistor Q is rendered conductive when a prescribed voltage is applied to the word line 20, a charge applied to the bit line 30 is stored in the capacitor Cs. In data reading, the field effect transistor Q is rendered conductive when a prescribed voltage is applied to the word line 20, the charge stored in the capacitor Cs is taken out via the bit line 30.
FIG. 5 is a fragmentary plan view illustrating a planar arrangement of a memory cell array portion of the DRAM of a folded bit line scheme. FIG. 5 illustrates four memory cells, and typically illustrates two of the memory cells respectively formed of two sets of field effect transistors and capacitors, Q1 and Cs1, Q2 and Cs2 which are formed on an operation region Al separated from the adjacent memory cells. The gate electrodes of the respective transistors Q1, Q2, Q3, Q4 are connected to the word lines 20 corresponding to the respective memory cells. The bit lines 30 are formed on the word lines 20 to be insulated from and intersecting the word lines 20. The bit lines 30 are connected to the memory cells through contact holes C1, C2, C3. A cross section taken along the line VI--VI of FIG. 5 is illustrated in processing steps in the FIGS. 6A-6M. A method of manufacturing the DRAM having conventional stacked capacitors will now be described. The DRAM having the stacked capacitors is, for example, disclosed in IEDM Digest of Technical Papers (1978), pp. 348-351 by M. Koyanagi et al. Further, a manufacturing method thereof is, for example, disclosed in Japanese Patent Laying Open No. 63-44756.
First of all, referring to FIG. 6A, an underlying oxide film 12 is formed on a P type silicon substrate 1 such as by a thermal oxidation method. A nitride film 13 is formed on the underlying oxide film 12 such as by chemical vapor deposition (CVD) method.
Next, referring to FIG. 6B, after a resist film is deposited on the nitride film 13, the nitride film 13 is selectively removed following a prescribed pattern. With the patterned nitride film 13 used as a mask, P type impurity ion, eg. boron ion is implanted into the P type silicon substrate 1 in a direction shown by arrows, at an acceleration voltage of approximately 10-200keV.
Furthermore, referring to FIG. 6C, by the thermal oxidation process performed with the nitride film 13 used as a mask, a field oxide film 4 for isolation is formed on the ion-implanted P type silicon substrate 1, and a P type impurity diffusion region 5 for channel stopper is formed beneath the field oxide film 4 for isolation by thermal diffusion of the implanted P type impurity ion.
Referring to FIG. 6D, the nitride film 13 and underlying oxide film 12 are then removed by etching.
As shown in FIG. 6E, an insulating film 17a made of an oxide film is formed by thermal oxidation, for example.
As shown in FIG. 6F, a polysilicon film 15 is deposited on the entire surface such as by the chemical vapor deposition method. Further, by employing SiH.sub.4, N.sub.2 O as a raw gas, a silicon oxide film 18a as an upper layer insulating film is deposited on the polysilicon film 15 at a temperature of 850.degree. C. by the chemical vapor deposition method. The silicon oxide film deposited by this method is called a high temperature oxide film (an HTO film).
As shown in FIG. 6G, a resist film 14 is then formed on the silicon oxide film 18a according to the prescribed pattern.
Referring to FIG. 6H, with the resist film 14 used as a mask, the silicon oxide film 18a, which is a high temperature oxide film is removed, such as by dry etching employing an etching gas including a CHF.sub.3 gas as its principal material, and the polysilicon film 15 is removed by dry etching employing an etching gas including CCl.sub.4 gas as its principal material. As described above, an upper layer insulating film 18 and a word line 20 as a gate electrode are formed. However, notches 20a are formed in the lower part of the word line 20 by the above described etching.
The resist film 14 is then removed as shown in FIG. 6I.
As shown in FIG. 6J, N type impurity diffusion regions 61a, 62a of low concentration are formed by implantation of N type impurity ion with the word line used as mask, and thereafter, a sidewall insulating film 19 is formed on the sidewall of the word line 20. N type impurity diffusion regions 61b, 62b of high concentration are formed by implantation of the N type impurity ion again, with the word line 20 and sidewall insulating film 19 used as masks. An N channel type MOS transistor having a LDD structure is formed as described above. That is, N type impurity diffusion regions 61, 62 are formed which are constituted by the N type impurity diffusion regions 61a, 62a of low concentration and the N type impurity diffusion regions 61b, 62b of high concentration to be source/drain regions.
Next, referring to FIG. 6K, a storage node 8 made of a conductive material such as polysilicon is selectively formed to connect with each of the N channel type MOS transistors.
Referring to FIG. 6L, a capacitor dielectric film 11 made of a silicon oxide film, a nitride film etc. is formed on the storage node 8. A cell plate 9 made of a conductive material such as polysilicon is formed on the capacitor dielectric film 11. As mentioned above, a stacked capacitor constituted by the storage node 8, the capacitor dielectric film 11 and the cell plate 9 is formed to connect with one N type impurity diffusion region 61 of the N channel MOS transistor.
Finally, as shown in FIG. 6M, after an interlayer insulating film 21 made of such as an oxide film, a contact hole C is made to connect with the other N type impurity diffusion region 62 of the N channel type MOS transistor. A bit line 30 made of such as an aluminum layer is formed to connect with the N type impurity diffusion region 62 through this contact hole C.
The DRAM having memory cells of the stacked capacitor structures is formed as described heretofore.
In the DRAM having memory cells of the conventional stacked capacitor structures, when the word line as a gate electrode and the upper layer insulating film formed thereon are selectively removed by employing the same mask, portions of the lower part of the word line are cut out to form notches therein. There is a problem that as the notches exist in the word line as a gate electrode, channel resistance increases in the operation of the MOS transistor. This results from the fact that since no impurity diffusion region is formed in a region directly beneath the notches formed in the lower part of the gate electrode, the region becomes a high resistance portion in the operation of the transistor, so that an inversion layer is hard to be formed. Therefore, there is a problem of decreased operation speed in the MOS transistor.